# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=amdgpu9.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX9-ERR %s

0xdf,0x00,0x00,0x02
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

# This is v_readfirstlane_b32 with an SGPR destination that does not fit the
# 7-bit scalar register encoding of the 8-bit VOP1 vdst field.
0x00,0x05,0xf4,0x7f
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

# These are v_add_f32_sdwa with a reserved value in one of the SDWA fields:
# 7 in a 3-bit sel field and 3 in the 2-bit dst_unused field.
0xf9,0x04,0x00,0x02,0x01,0x07,0x06,0x06
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

0xf9,0x04,0x00,0x02,0x01,0x1e,0x06,0x06
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

0xf9,0x04,0x00,0x02,0x01,0x06,0x07,0x06
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

0xf9,0x04,0x00,0x02,0x01,0x06,0x06,0x07
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

# v_cvt_f64_i32_dpp and v_ceil_f64_dpp: 64-bit VGPR DPP needs gfx90a+.
0xfa,0x08,0x00,0x7e,0x02,0x4e,0x00,0xff
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

0xfa,0x30,0x00,0x7e,0x02,0x4e,0x00,0xff
# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
