# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=amdgpu9.08-amd-amdhsa -disassemble -show-encoding < %s 2>&1 | FileCheck --implicit-check-not=warning: %s
# RUN: llvm-mc -triple=amdgpu9.0a-amd-amdhsa -disassemble -show-encoding < %s 2>&1 | FileCheck --implicit-check-not=warning: %s
# RUN: llvm-mc -triple=amdgpu9.42-amd-amdhsa -disassemble -show-encoding < %s 2>&1 | FileCheck --implicit-check-not=warning: %s
# RUN: llvm-mc -triple=amdgpu9.50-amd-amdhsa -disassemble -show-encoding < %s 2>&1 | FileCheck --implicit-check-not=warning: %s

# The AV and AGPR source operands below only accept vector registers, so an
# encoding naming an SGPR or an inline constant must be rejected. -show-encoding
# is required: re-encoding the decoded instruction is what used to assert on the
# non-register operand.

# This is v_mfma_f32_16x16x1_4b_f32 with s0 as src0.
0x00,0x00,0xc1,0xd3,0x00,0x00,0x02,0x04
# CHECK: :[[@LINE-1]]:1: warning: invalid instruction encoding

# This is v_mfma_f32_16x16x1_4b_f32 with the inline constant 0 as src1.
0x00,0x00,0xc1,0xd3,0x00,0x01,0x01,0x04
# CHECK: :[[@LINE-1]]:1: warning: invalid instruction encoding

# This is v_accvgpr_read_b32 with s0 as src0.
0x02,0x40,0xd8,0xd3,0x00,0x00,0x00,0x18
# CHECK: :[[@LINE-1]]:1: warning: invalid instruction encoding

# This is v_accvgpr_read_b32 with the inline constant 0 as src0.
0x02,0x40,0xd8,0xd3,0x80,0x00,0x00,0x18
# CHECK: :[[@LINE-1]]:1: warning: invalid instruction encoding
